Such a storage device is very suitable for many applications and as such will be present arranged in rows and columns in devices requiring non-volatile memory. They are e.g. known as (E)EPROM=(Electrically) Erasable and Programmable Read Only Memory. Storage of charge on the floating gate allows the threshold voltage (VT) to be electrically altered between a low and a high value to represent logic 0 and 1, respectively. Such a storage device typically also comprises a control gate for controlling the storage device in read and write mode.
The reduction of the feature sizes of semiconductor devices poses design challenges for the integration of such storage devices in future semiconductor technologies. For instance, conventional designs of such a storage device in which the control gate is located on top of the floating gate require a relatively high voltage for programming the storage device, which makes such arrangements unsuitable for use in semiconductor technologies having a relatively small feature size because such technologies cannot withstand these relatively high voltages.
This problem has been addressed for instance in U.S. Pat. No. 7,276,759, in which a polysilicon control gate is placed adjacent to a poly-silicon floating gate, such that these two gates are capacitively coupled through a dielectric material in between these two gates. As a consequence, the floating gate can be programmed at lower voltages such that this arrangement is suitable for application in semiconductor technologies having reduced feature sizes.
A disadvantage of the known device is that its applicability in deep sub-micron technologies is expected to be limited because of the design rules imposed on the spacing of polysilicon structures therein, which imposes a lower limit on the size of such a device. Also, this approach requires the separation of multiple poly-Si layers by special dielectrics as well as the careful alignment of the various layers, thus adding to the cost of such a device.